1. Field of the Invention
The present invention relates to telecommunications. More particularly, the present invention relates to the passing of high speed Asynchronous Transfer Mode (ATM) data over a standardized Universal Test and Operations Physical Interface for ATM (UTOPIA) bus.
2. State of the Art
Perhaps the most awaited, and now fastest growing technology in the field of telecommunications in the 1990""s is known as ATM technology. ATM is providing a mechanism for removing performance limitations of local area networks (LANs) and wide area networks (WANs) and providing data transfers at a speed of on the order of gigabits/second. Within the ATM technology, a commonly used interface specification between chips on a board for passing ATM cells is the UTOPIA interface. The UTOPIA interface is specified in ATM Forum standard specification af_phyxe2x80x940039.000 (UTOPIA Level 2, Version 1, June 1995) which is hereby incorporated by reference herein in its entirety.
Prior art FIG. 1 shows a typical intraboard ATM application of the UTOPIA interface. In particular, on a single board 11, an ATM layer chip 15 is coupled to a physical layer chip 17 which is shown to include a plurality of physical devices 19a-19d. The ATM layer chip 15 and physical layer chip 17 utilize the UTOPIA interface, which includes a five bit address bus 21, a seventeen bit data/start-of-cell bus 23 (sixteen bits used for data), an enable line (one bit signal) 25, and a cell available line (one bit signal) 27. The physical layer chip 17 is provided with two address registers 31, 33, a multiplexer 35 and a demultiplexer 37.
The application shown in prior art FIG. 1 functions in the following manner using the timing shown in prior art FIG. 2. The ATM layer chip 17 utilizes a clock such as a 50 MHz clock, and polls the physical layer devices for data by sequentially sending an address (of a physical device), followed by a NULL address (all ones), followed by a next address, followed by a NULL address, followed by a next address, etc. According to the UTOPIA interface standard, when a physical device is in a state in which it can receive data, it provides a cell available signal to the multiplexer 35. The address received by the address register 31 is used as a select for the multiplexer 35. Thus, when a particular physical device is selected, if it can receive data, a cell available signal is provided back to the ATM layer chip over the cell available line 27. After polling is completed, the ATM layer chip 17 (or a processor coupled thereto) determines which physical device (address) is to receive the data. It then sends the address of the recipient over the address bus 21 in conjunction with an enable signal over line 25. The selected address is clocked by the enable line into the address register 33. The address register 33 is used as a control for the demultiplexer 37 which selects the physical device 19 which is to receive the data. The data (including the forty-eight byte payload of a cell) is then sequentially forwarded over the data bus 23 while a next sequential polling is performed over the address bus.
While the UTOPIA interface has proved to be very useful for interfacing two chips on a single board (intra-board), the UTOPIA interface has not been applicable across boards (inter-board) apparently because of both timing and xe2x80x9chot insertionxe2x80x9d problems which can be encountered. In particular, OC-12 (622 Mbps) and four-port OC-3 (155 Mbps) standards require that the UTOPIA interface operate at up to a 50 MHz clock rate. However, many existing devices with UTOPIA interfaces have large propagation delays and inadequate drive capability for backplane applications (i.e., inter-board connections) operating at this clock rate. In addition, in inter-board applications, it is possible that one board is already functioning as the other board is being inserted (xe2x80x9chot insertionxe2x80x9d), leading to the possibility of electrical shorting and damaging of components, and the provided UTOPIA interface standard does not provide a mechanism to deal with this problem. Thus, the UTOPIA specification is inadequate to cover inter-board interfaces. Indeed, the ATM Forum Standard committee apparently understood this problem and specifically stated in the standard that the backplane applications of the UTOPIA bus are xe2x80x9cfor further studyxe2x80x9d.
It is therefore an object of the invention to provide a UTOPIA interface enhancement which permits inter-board UTOPIA interfaces to function properly.
It is another object of the invention to provide a modified UTOPIA interface which is hot insertion tolerant.
In accord with the objects of the invention, a modified UTOPIA interface for inter-board applications is provided where the address timing generated by a polling master is extended to be two clock cycles long with no NULL address being driven onto the address line in between addresses. In addition, additional output and input circuitry is provided in conjunction with the master and user ATM boards to accommodate hot insertion and to help drive the circuit. The output circuitry provided in conjunction with the master preferably includes an outgoing address latch and address latch control associated with the address bus, and registers associated with the enable signal and the data bus. The input circuitry preferably provided in conjunction with the master includes a buffer on the cell available signal. The input circuitry preferably provided in conjunction with the user device(s) includes buffers on the address bus, the enable signal and the data bus. A remapping function is also preferably provided in associated with the user board which permits the user board to map received addresses into desired addresses. With the extended address timing and the provided circuitry, a workable inter-board hot-insertable UTOPIA interface is established.
Additional objects and advantages of the invention will become apparent to those skilled in the art upon reference to the detailed description taken in conjunction with the provided figures.